/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright (C) 2022 Renesas Electronics Corp.
 */
#ifndef __DT_BINDINGS_CLOCK_R9A07G043F_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R9A07G043F_CPG_MSSR_H__

#include <dt-bindings/clock/renesas-cpg-mssr.h>

/* r9a07g043f CPG Core Clocks */
#define R9A07G043F_CLK_I		0
#define R9A07G043F_CLK_I2		1
#define R9A07G043F_CLK_G		2
#define R9A07G043F_CLK_S0		3
#define R9A07G043F_CLK_S1		4
#define R9A07G043F_CLK_SPI0		5
#define R9A07G043F_CLK_SPI1		6
#define R9A07G043F_CLK_SD0		7
#define R9A07G043F_CLK_SD1		8
#define R9A07G043F_CLK_M0		9
#define R9A07G043F_CLK_M1		10
#define R9A07G043F_CLK_M2		11
#define R9A07G043F_CLK_M3		12
#define R9A07G043F_CLK_M4		13
#define R9A07G043F_CLK_HP		14
#define R9A07G043F_CLK_TSU		15
#define R9A07G043F_CLK_ZT		16
#define R9A07G043F_CLK_P0		17
#define R9A07G043F_CLK_P1		18
#define R9A07G043F_CLK_P2		19
#define R9A07G043F_CLK_AT		20
#define R9A07G043F_OSCCLK		21

/* r9a07g043f Module Clocks */
#define R9A07G043F_CLK_IA55		0
#define R9A07G043F_CLK_SYC		1
#define R9A07G043F_CLK_DMAC		2
#define R9A07G043F_CLK_MTU		3
#define R9A07G043F_CLK_ETH0		4
#define R9A07G043F_CLK_ETH1		5
#define R9A07G043F_CLK_I2C0		6
#define R9A07G043F_CLK_I2C1		7
#define R9A07G043F_CLK_I2C2		8
#define R9A07G043F_CLK_I2C3		9
#define R9A07G043F_CLK_SCIF0		10
#define R9A07G043F_CLK_SCIF1		11
#define R9A07G043F_CLK_SCIF2		12
#define R9A07G043F_CLK_SCIF3		13
#define R9A07G043F_CLK_SCIF4		14
#define R9A07G043F_CLK_SCI0		15
#define R9A07G043F_CLK_SCI1		16
#define R9A07G043F_CLK_GPIO		17
#define R9A07G043F_CLK_SDHI0		18
#define R9A07G043F_CLK_SDHI1		19
#define R9A07G043F_CLK_USB0		20
#define R9A07G043F_CLK_USB1		21
#define R9A07G043F_CLK_CANFD		22
#define R9A07G043F_CLK_SSI0		23
#define R9A07G043F_CLK_SSI1		24
#define R9A07G043F_CLK_SSI2		25
#define R9A07G043F_CLK_SSI3		26
#define R9A07G043F_CLK_OSTM0		27
#define R9A07G043F_CLK_OSTM1		28
#define R9A07G043F_CLK_OSTM2		29
#define R9A07G043F_CLK_WDT0		30
#define R9A07G043F_CLK_WDT_PON		31
#define R9A07G043F_CLK_SRC		32
#define R9A07G043F_CLK_RSPI0		33
#define R9A07G043F_CLK_RSPI1		34
#define R9A07G043F_CLK_RSPI2		35
#define R9A07G043F_CLK_ADC		36
#define R9A07G043F_CLK_TSU_PCLK		37
#define R9A07G043F_CLK_SPI		38

#endif /* __DT_BINDINGS_CLOCK_R9A07G043F_CPG_H__ */
